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Jayant Baliga
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    Fundamentals of Power Semiconductor Devices

    Weitere Titel des Verlages

    Fundamentals of Power Semiconductor Devices

    Autoren:

    Verlag:
    Springer-Verlag   Weitere Titel dieses Verlages anzeigen

    Erschienen: Oktober 2008
    Seiten: 1072
    Sprache: Englisch
    Preis: 165.84 €
    Maße: 235x155x69
    Einband: Gebundene Ausgabe
    ISBN: 9780387473130

    Inhaltsverzeichnis

    Contents
    Prefacevii
    Chapter 1 Introduction1
    1.1Ideal and Typical Power Switching Waveforms3
    1.2Ideal and Typical Power Device Characteristics5
    1.3Unipolar Power Devices8
    1.4Bipolar Power Devices10
    1.5MOS-Bipolar Power Devices11
    1.6Ideal Drift Region for Unipolar Power Devices14
    1.7Charge-Coupled Structures: Ideal Specific On-Resistance16
    1.8Summary21
    Problems21
    References22
    Chapter 2 Material Properties and Transport Physics23
    2.1Fundamental Properties23
    2.1.1Intrinsic Carrier Concentration25
    2.1.2Bandgap Narrowing26
    2.1.3Built-in Potential30
    2.1.4Zero-Bias Depletion Width32
    2.1.5Impact Ionization Coefficients32
    2.1.6Carrier Mobility34
    2.2Resistivity51
    2.2.1Intrinsic Resistivity51
    2.2.2Extrinsic Resistivity51
    2.2.3Neutron Transmutation Doping55
    2.3Recombination Lifetime59
    2.3.1Shockley-Read-Hall Recombination60
    2.3.2Low-Level Lifetime63
    2.3.3Space-Charge Generation Lifetime65
    2.3.4Recombination Level Optimization66
    2.3.5Lifetime Control75
    2.3.6Auger Recombination80
    2.4Ohmic Contacts82
    2.5Summary84
    Problems84
    References86
    Chapter 3 Breakdown Voltage91
    3.1Avalanche Breakdown92
    3.1.1Power Law Approximations for the Impact Ionization Coefficients92
    3.1.2Multiplication Coefficient94
    3.2Abrupt One-Dimensional Diode95
    3.3Ideal Specific On-Resistance100
    3.4Abrupt Punch-Through Diode101
    3.5Linearly Graded Junction Diode104
    3.6Edge Terminations107
    3.6.1Planar Junction Termination108
    3.6.2Planar Junction with Floating Field Ring120
    3.6.3Planar Junction with Multiple Floating Field Rings130
    3.6.4Planar Junction with Field Plate132
    3.6.5Planar Junction with Field Plates and Field Rings137
    3.6.6Bevel Edge Terminations137
    3.6.7Etch Terminations148
    3.6.8Junction Termination Extension149
    3.7Open-Base Transistor Breakdown155
    3.7.1Composite Bevel Termination159
    3.7.2Double-Positive Bevel Termination159
    3.8Surface Passivation162
    3.9Summary162
    Problems163
    References164
    Chapter 4 Schottky Rectifiers167
    4.1Power Schottky Rectifier Structure168
    4.2Metal-Semiconductor Contact169
    4.3Forward Conduction171
    4.4Reverse Blocking179
    4.4.1Leakage Current180
    4.4.2Schottky Barrier Lowering181
    4.4.3Prebreakdown Avalanche Multiplication184
    4.4.4Silicon Carbide Rectifiers185
    4.5Device Capacitance187
    4.6Thermal Considerations188
    4.7Fundamental Tradeoff Analysis192
    4.8Device Technology194
    4.9Barrier Height Adjustment194
    4.10Edge Terminations197
    4.11Summary198
    Problems199
    References200
    Chapter 5 P-i-N Rectifiers203
    5.1One-Dimensional Structure204
    5.1.1Recombination Current205
    5.1.2Low-Level Injection Current206
    5.1.3High-Level Injection Current208
    5.1.4Injection into the End Regions217
    5.1.5Carrier-Carrier Scattering Effect219
    5.1.6Auger Recombination Effect219
    5.1.7Forward Conduction Characteristics221
    5.2Silicon Carbide P-i-N Rectifiers230
    5.3Reverse Blocking232
    5.4Switching Performance236
    5.4.1Forward Recovery236
    5.4.2Reverse Recovery244
    5.5P-i-N Rectifier Structure with Buffer Layer262
    5.6Nonpunch-Through P-i-N Rectifier Structure263
    5.7P-i-N Rectifier Tradeoff Curves270
    5.8Summary274
    Problems275
    References276
    Chapter 6 Power MOSFETs279
    6.1Ideal Specific On-Resistance280
    6.2Device Cell Structure and Operation282
    6.2.1The V-MOSFET Structure283
    6.2.2The VD-MOSFET Structure284
    6.2.3The U-MOSFET Structure285
    6.3Basic Device Characteristics286
    6.4Blocking Voltage289
    6.4.1Impact of Edge Termination289
    6.4.2Impact of Graded Doping Profile290
    6.4.3Impact of Parasitic Bipolar Transistor291
    6.4.4Impact of Cell Pitch293
    6.4.5Impact of Gate Shape296
    6.4.6Impact of Cell Surface Topology298
    6.5Forward Conduction Characteristics300
    6.5.1MOS Interface Physics301
    6.5.2MOS Surface Charge Analysis305
    6.5.3Maximum Depletion Width310
    6.5.4Threshold Voltage311
    6.5.5Channel Resistance321
    6.6Power VD-MOSFET On-Resistance327
    6.6.1Source Contact Resistance329
    6.6.2Source Region Resistance330
    6.6.3Channel Resistance331
    6.6.4Accumulation Resistance332
    6.6.5JFET Resistance333
    6.6.6Drift Region Resistance335
    6.6.7N+Substrate Resistance339
    6.6.8Drain Contact Resistance339
    6.6.9Total On-Resistance340
    6.7Power VD-MOSFET Cell Optimization343
    6.7.1Optimization of Gate Electrode Width343
    6.7.2Impact of Breakdown Voltage345
    6.7.3Impact of Design Rules348
    6.7.4Impact of Cell Topology350
    6.8Power U-MOSFET On-Resistance358
    6.8.1Source Contact Resistance359
    6.8.2Source Region Resistance361
    6.8.3Channel Resistance361
    6.8.4Accumulation Resistance362
    6.8.5Drift Region Resistance363
    6.8.6N+Substrate Resistance364
    6.8.7Drain Contact Resistance365
    6.8.8Total On-Resistance365
    6.9Power U-MOSFET Cell Optimization368
    6.9.1Orthogonal P-Base Contact Structure368
    6.9.2Impact of Breakdown Voltage371
    6.9.3Ruggedness Improvement372
    6.10Square-Law Transfer Characteristics373
    6.11Superlinear Transfer Characteristics377
    6.12Output Characteristics381
    6.13Device Capacitances385
    6.13.1Basic MOS Capacitance386
    6.13.2Power VD-MOSFET Structure Capacitances389
    6.13.3Power U-MOSFET Structure Capacitances399
    6.13.4Equivalent Circuit408
    6.14Gate Charge409
    6.14.1Charge Extraction409
    6.14.2Voltage and Current Dependence417
    6.14.3VD-MOSFET vs. U-MOSFET Structure421
    6.14.4Impact of VD-MOSFET and U-MOSFET Cell Pitch423
    6.15Optimization for High Frequency Operation426
    6.15.1Input Switching Power Loss427
    6.15.2Output Switching Power Loss432
    6.15.3Gate Propagation Delay434
    6.16Switching Characteristics436
    6.16.1Turn-On Transient437
    6.16.2Turn-Off Transient440
    6.16.3Switching Power Losses443
    6.16.4[dV/dt] Capability443
    6.17Safe Operating Area447
    6.17.1Bipolar Second Breakdown449
    6.17.2MOS Second Breakdown451
    6.18Integral Body Diode452
    6.18.1Reverse Recovery Enhancement453
    6.18.2Impact of Parasitic Bipolar Transistor453
    6.19High-Temperature Characteristics454
    6.19.1Threshold Voltage454
    6.19.2On-Resistance455
    6.19.3Saturation Transconductance456
    6.20Complementary Devices457
    6.20.1The p-Channel Structure458
    6.20.2On-Resistance458
    6.20.3Deep-Trench Structure459
    6.21Silicon Power MOSFET Process Technology460
    6.21.1Planar VD-MOSFET Process460
    6.21.2Trench U-MOSFET Process462
    6.22Silicon Carbide Devices465
    6.22.1The Baliga-Pair Configuration465
    6.22.2Planar Power MOSFET Structure476
    6.22.3Shielded Planar Power MOSFET Structures481
    6.22.4Shielded Trench-Gate Power MOSFET Structure489
    6.23Summary498
    Problems499
    References503
    Chapter 7 Bipolar Junction Transistors507
    7.1Power Bipolar Junction Transistor Structure508
    7.2Basic Operating Principles510
    7.3Static Blocking Characteristics513
    7.3.1Open-Emitter Breakdown Voltage514
    7.3.2Open-Base Breakdown Voltage514
    7.3.3Shorted Base-Emitter Operation516
    7.4Current Gain520
    7.4.1Emitter Injection Efficiency522
    7.4.2Emitter Injection Efficiency with Recombination in the Depletion Region526
    7.4.3Emitter Injection Efficiency with High-Level Injection in the Base528
    7.4.4Base Transport Factor533
    7.4.5Base Widening at High Collector Current Density536
    7.5Emitter Current Crowding550
    7.5.1Low-Level Injection in the Base551
    7.5.2High-Level Injection in the Base555
    7.5.3Emitter Geometry559
    7.6Output Characteristics560
    7.7On-State Characteristics565
    7.7.1Saturation Region566
    7.7.2Quasisaturation Region571
    7.8Switching Characteristics574
    7.8.1Turn-On Transition575
    7.8.2Turn-Off Transition588
    7.9Safe Operating Area607
    7.9.1Forward-Biased Second Breakdown608
    7.9.2Reverse-Biased Second Breakdown611
    7.9.3Boundary for Safe Operating Area615
    7.10Darlington Configuration616
    7.11Summary619
    Problems619
    References621
    Chapter 8 Thyristors625
    8.1Power Thyristor Structure and Operation628
    8.2Blocking Characteristics631
    8.2.1Reverse-Blocking Capability632
    8.2.2Forward-Blocking Capability636
    8.2.3Cathode Shorting641
    8.2.4Cathode Shorting Geometry644
    8.3On-State Characteristics651
    8.3.1On-State Operation652
    8.3.2Gate-Triggering Current654
    8.3.3Holding Current657
    8.4Switching Characteristics662
    8.4.1Turn-On Time663
    8.4.2Gate Design671
    8.4.3Amplifying Gate Design672
    8.4.4[dV/dt] Capability675
    8.4.5Turn-Off Process683
    8.5Light-Activated Thyristors685
    8.5.1[dI/dt] Capability686
    8.5.2Gate Region Design687
    8.5.3Optically Generated Current Density688
    8.5.4Amplifying Gate Design690
    8.6Self-Protected Thyristors691
    8.6.1Forward Breakdown Protection691
    8.6.2[dV/dt] Turn-On Protection694
    8.7The Gate Turn-Off Thyristor Structure698
    8.7.1Basic Structure and Operation698
    8.7.2One-Dimensional Turn-Off Criterion701
    8.7.3One-Dimensional Storage Time Analysis703
    8.7.4Two-Dimensional Storage Time Model704
    8.7.5One-Dimensional Voltage Rise Time Model706
    8.7.6One-Dimensional Current Fall Time Model709
    8.7.7Switching Energy Loss721
    8.7.8Maximum Turn-Off Current722
    8.7.9Cell Design and Layout725
    8.8The Triac Structure726
    8.8.1Basic Structure and Operation728
    8.8.2Gate-Triggering Mode 1729
    8.8.3Gate-Triggering Mode 2730
    8.8.4[dV/dt] Capability731
    8.9Summary733
    Problems733
    References735
    Chapter 9 Insulated Gate Bipolar Transistors737
    9.1Basic Device Structures741
    9.2Device Operation and Output Characteristics745
    9.3Device Equivalent Circuit748
    9.4Blocking Characteristics748
    9.4.1Symmetric Structure Forward-Blocking Capability748
    9.4.2Symmetric Structure Reverse-Blocking Capability753
    9.4.3Symmetric Structure Leakage Current754
    9.4.4Asymmetric Structure Forward-Blocking Capability760
    9.4.5Asymmetric Structure Reverse-Blocking Capability767
    9.4.6Asymmetric Structure Leakage Current769
    9.5On-State Characteristics776
    9.5.1On-State Model776
    9.5.2On-State Carrier Distribution: Symmetric Structure783
    9.5.3On-State Voltage Drop: Symmetric Structure791
    9.5.4On-State Carrier Distribution: Asymmetric Structure796
    9.5.5On-State Voltage Drop: Asymmetric Structure803
    9.5.6On-State Carrier Distribution: Transparent Emitter Structure808
    9.5.7On-State Voltage Drop: Transparent Emitter Structure813
    9.6Current Saturation Model815
    9.6.1Carrier Distribution: Symmetric Structure820
    9.6.2Output Characteristics: Symmetric Structure828
    9.6.3Output Resistance: Symmetric Structure833
    9.6.4Carrier Distribution: Asymmetric Structure834
    9.6.5Output Characteristics: Asymmetric Structure844
    9.6.6Output Resistance: Asymmetric Structure848
    9.6.7Carrier Distribution: Transparent Emitter Structure849
    9.6.8Output Characteristics : Transparent Emitter Structure853
    9.6.9Output Resistance: Transparent Emitter Structure855
    9.7Switching Characteristics856
    9.7.1Turn-On Physics: Forward Recovery857
    9.7.2Turn-Off Physics: No-Load Conditions865
    9.7.3Turn-Off Physics: Resistive Load867
    9.7.4Turn-Off Physics: Inductive Load876
    9.7.5Energy Loss per Cycle904
    9.8Power Loss Optimization907
    9.8.1Symmetric Structure907
    9.8.2Asymmetric Structure909
    9.8.3Transparent Emitter Structure911
    9.8.4Comparison of Tradeoff Curves912
    9.9Complementary (P-Channel) Structure913
    9.9.1On-State Characteristics915
    9.9.2Switching Characteristics919
    9.9.3Power Loss Optimization919
    9.10Latch-Up Suppression920
    9.10.1Deep P+Diffusion922
    9.10.2Shallow P+Layer928
    9.10.3Reduced Gate Oxide Thickness931
    9.10.4Bipolar Current Bypass936
    9.10.5Diverter Structure939
    9.10.6Cell Topology943
    9.10.7Latch-Up Proof Structure948
    9.11Safe Operating Area951
    9.11.1Forward-Biased Safe Operating Area952
    9.11.2Reverse-Biased Safe Operating Area956
    9.11.3Short-Circuit Safe Operating Area960
    9.12Trench-Gate Structure966
    9.12.1Blocking Mode967
    9.12.2On-State Carrier Distribution969
    9.12.3On-State Voltage Drop971
    9.12.4Switching Characteristics973
    9.12.5Safe Operating Area974
    9.12.6Modified Structures978
    9.13Blocking Voltage Scaling980
    9.13.1N-Base Design981
    9.13.2Power MOSFET Baseline982
    9.13.3On-State Characteristics982
    9.13.4Tradeoff Curve985
    9.14High Temperature Operation986
    9.14.1On-State Characteristics986
    9.14.2Latch-Up Characteristics989
    9.15Lifetime Control Techniques991
    9.15.1Electron Irradiation991
    9.15.2Neutron Irradiation993
    9.15.3Helium Irradiation993
    9.16Cell Optimization994
    9.16.1Planar-Gate Structure995
    9.16.2Trench-Gate Structure999
    9.17Reverse Conducting Structure1006
    9.18Summary1014
    Problems1015
    References1020
    Chapter 10 Synopsis1027
    10.1Typical H-Bridge Topology1027
    10.2Power Loss Analysis1029
    10.3Low DC Bus Voltage Applications1032
    10.4Medium DC Bus Voltage Applications1037
    10.5High DC Bus Voltage Applications1041
    10.6Summary1045
    Problems1045
    References1047
    Author's Biography1049
    Index1053